Bias circuits are used to provide bias voltages, which may be used to bias PMOS and NMOS transistors. The bias circuits provide the bias voltages when they are enabled by enablement signals. There are various types of bias circuits with different designs.
One of the commonly used bias circuits includes a series of diodes, which may be formed of transistors with the gates connected to the respective drains. The series of diode connected devices are used to start up the bias circuit that usually has a pair of PMOS and/or NMOS transistors forming a current mirror. For these diode-connected types of bias circuits, there is a serious trade-off between leakage current and enablement speed. To enhance enablement speed, short channel diode-connected device is preferable; on the other hand to prevent leakage current from flowing through the diodes, it is desirable to use long channel transistors to form the diodes, and/or to increase the number of the serially connected diodes. However, this causes a reduction in the turn-on speed of the transistors that form the current mirror, and a reduction in the enablement speed of the bias circuit. Conversely, if short channel transistors are used, although the enablement speed is increased, the leakage current increases either. Furthermore, the rising in VCC voltages, which are the power supply voltages of the bias circuits, may also result in the increase in the leakage currents. Typically, these types of bias circuits have very low enablement speed, often in the order of micro-seconds.
In a second conventional bias circuit, an NMOS transistor and a PMOS transistor are inserted into the two signal paths of a current mirror of a bias circuit. The gate of the NMOS transistor is connected to VCC, and the gate of the PMOS transistor is connected to an electrical ground. The other NMOS transistor and the PMOS transistor help to balance loading and the layout pattern to avoid mismatch issues. Typically, this type of bias circuits has a very high enablement speed, often in the order of tens of nano-seconds. However, this type of bias circuits is prone to the disturbance from the power supply, which disturbance is coupled from the VCC and the electrical ground to the gates of the NMOS transistor and the PMOS transistor. Accordingly, the disturbance is adversely coupled into the signal paths.